Multiple path, self-routing switching network for switching asynchronous time division multiplex cells

ABSTRACT

A multiple path, self-routing switching network for switching asynchronous time division multiplex data cells includes input ports (pi1, pi64 . . . ), output ports (po1, po64 . . . ) and switching elements (TSi1, TSi16 . . . ) arranged in a number of stages of interconnected switching elements, each switching element having inlets and outlets and being constructed to transfer a data cell received at one of its inlets, to one or more of its outlets, according to routing data associated with said cells. Each switching element of at least one stage of the network has at least three outlets, arranged in groups of outlets of one or more determined outlets. Using routing data associated with a data cell received at any one of its inlets, the switching element (TSi1, TSi16 . . . ) identifies a set of one or more of said groups of outlets and to transfer said received cell to an outlet of each group of outlets of the selected set.

This invention relates to a multiple path, self-routing switchingnetwork for switching asynchronous time division multiplex cells.

A switching network, in its widest structural definition, comprisesinput ports to which are connected input connections, output ports towhich are connected output connections, switching elements disposedbetween these input ports and these output ports, arranged in one ormore stages and interconnected by links. The input ports of theswitching network are associated with the inlets of switching elementsof a first stage, while the output ports are associated with the outletsof switching elements of a last stage. The outlets of the switchingelements of said first stage are connected by links, possibly by meansof intermediate switching element stages, to the inlets of the switchingelements of said last stage. The links generally comprise one or moreindependent connections, each connecting an outlet of a switchingelement to an inlet of another switching element or the same switchingelement.

Such a switching network is said to be a multiple path network when itoffers more than one switchpath between any one input port and any oneoutput port. In this case, identification of an input port and an outputport is not sufficient to determine a path from one to the other. Thereis still a choice to be made between the multiple paths offered by theswitching network between this input port and this output port.

Such a network is said to be self-routing, in the broadest sense of theterm, when it is such that a switchpath is determined in a switchingnetwork not only by means of routing information containing the implicitor explicit identification of an input port and that of an output portof the switching network, but also by a routing decision specific to theswitching network.

The self-routing facility introduced in the switching network thusprovides an independent means for solving the routing problem posed bymultiple path networks when the routing is defined only byidentification of an input port and an output port.

Multiple path, connection-oriented, self-routing switching networks arewell known in synchronous time division multiplex channel switching orcircuit switching. In such networks, the connection setup or routingprocess is accomplished once, at the beginning of a call, and determinesa switchpath the elements of which, initially free, are then occupied bythe call, and therefore become unavailable for other calls. Theswitchpaths set up therefore cause a risk of blocking through a lack ofchannels when searching for a new switchpath. The switching processapplied in these known switching networks generally encompasses all or amajor part of the switching network. It is therefore complex andrequires a relatively long time lapse, in terms of individual controloperations to establish the connection. On the other hand, this timelapse is very short, compared with the duration of the call and is nottherefore prejudicial to the communication efficiency of the switchingnetwork.

Cells, also called packets, are units of digital information comprisingin particular a tag containing information for identifying thedestination of the cell and call data.

Cells are of fixed length or variable length. In the latter case, thecell is transferred in the form of an uninterrupted sequence of a numberof relatively small fixed length sub-cells enabling internal transfer,storage in memory or in registers and sub-cell processing functions tobe optimised.

In an asynchronous time division multiplex cell transmission system, thecells of several calls, transmitted over the same connection, followeach other in any order and cells relative to a particular call aretransmitted at irregular intervals.

Taking into account the characteristics of asynchronous time divisionmultiplex cell transmission, an asynchronous time division multiplexcell switching network is generally a switching network constructed toswitch such cells individually, in such a way that a switchpath is foundfor each of them, to route it from an input port of the network to atleast one output port. In this case, a "cell-oriented" switching networkenables a pathfinding and selection process to be performed for eachindividual cell. In addition, it is also commonly accepted that, in thistype of network, it is advisable to make provision, not only forconventional routing, referred to as point-to-point, from one input portto one output port, but also at least point-to-multipoint routing,between one input port and a number of output ports.

However, a preliminary connection setup process, such as that justdescribed for asynchronous time division multiplex channel or circuitswitching networks, although it is in principle also applicable toasynchronous time division multiplex cell switching, neverthelesspresents a number of disadvantages, such as complex management of thebit rates of connections set up over each internal link of the networkand too long a time lapse for setting up data connections.

Multiple path, connection-oriented, self-routing switching networksknown in synchronous time division multiplex channel switching orcircuit switching do not therefore provide an optimum solution forasynchronous time division multiplex cell switching.

Those skilled in the art therefore turned to specific switching networksin which the switching process including pathfinding takes place stageby stage for each individual cell, therefore without preliminary setupand marking of a connection at the beginning of a call.

A description of an example of a switching network of this type will befound in the article "Design of a Broadcast Packet Network" by J. S.Turner, published in "Proceedings of IEEE INFOCOM '86", Fifth AnnualConference, "Computers and Communications Integration Design, Analysis,Management", pages 668 to 673.

Such a network comprises, from input ports to output ports, stagesspecialising in the replication of cells necessary forpoint-to-multipoint calls, stages specialising in the distribution ofcells, to mix the cells from the different inlets and to obtain equal,stable average bit rates per link, as far as it is statisticallypossible, and stages specialising in selective routing to the outputports. This network is constructed using switching elements with twoinlets and two outlets only. A small buffer memory for two cells isprovided at each switching element inlet. When a cell must use an outletwhich is not available, because another cell is already being forwardedover this outlet, the inlet can temporarily store the un-forwarded cell.

Such a network has disadvantages and limitations such as, in particular:

- a large number of stages when the number of input and output ports ishigh,

- limited efficiency through the storage of cells at inlets when outletsare busy,

- a certain difficulty in the implementation of extensions, due amongstother things to the large number of stages,

- the existence of cell replication stages, causing an additional cost,

- a certain sensitivity to the process of arrival of cells at each inputport, which is not completely overcome by the use of distribution stagesand which therefore affects the performance of the switching network,etc.

The object of this invention is an asynchronous, cell-oriented,self-routing, time division multiplex cell switching network notsuffering, or at least suffering in only a much smaller measure, fromthe above-mentioned disadvantages and limitations.

The switching network of this invention is characterised in that:

- each switching element of at least of one stage of the network has atleast three outlets,

- these outlets are arranged in groups of outlets called routing groups,

- a group of outlets comprises one or more determined outlets,

- on the basis of routing information associated with a fixed orvariable length cell received at any one of its inlets, the switchingelement is constructed to identify a set comprising one or more of saidoutlet groups of outlets, a copy of the cell being transferred to eachof the identified outlet groups,

- the switching element is constructed to transfer said received cell toa selected outlet of the outlets of the single group of said set, or oneoutlet per group of the outlets of said set, each selected from theoutlets of the group to which it belongs.

This network therefore consists, in at least one of its stages, ofswitching elements which, through the establishment of groups ofdetermined outlets, of which one outlet is selected each time, procurenot only a selective routing, but also effect a distribution of thecells over the different outlets of a routing group. In addition, thepossible routing to an outlet of each of several groups implements thereplication of cells necessary in the case of point-to-multipointrouting. Thus, as will be seen, such a switching element lends itself tothe implementation of integrated switching networks in which thespecialisation of parts of the switching network disappears. The moreoutlets per group the switching element contains, the better thedistribution, because the greater will be the number of paths offered toa cell, which also tends to reduce blocking through shortage ofavailable outlets, or to increase the routing efficiency of theswitching element and therefore the whole switching network. Similarly,the switching element is then less sensitive to the arrival process ofthe cells, since the cells from a particular inlet are routed by amultiplicity of different paths at each stage.

In a multistage switching network, it will be possible to arrange thatthe switching elements of at least two stages have the characteristicsindicated; the arrangement of the outlets in groups is not thennecessarily the same in each of these at least two stages and theswitching elements of each of these stages are constructed for each tohold its own routing parameters derived from position information.

Such arrangements will enable the respective location of its switchingelements in the switching network to be taken into account in thearrangement of their outlets in groups and in particular the fact thatthe arrangement of links between successive pairs of stages is notnecessarily the same.

According to another characteristic of the invention, said routinginformation is interpreted in each stage to determine the mode oftransferring a received cell to the outlets of the switching element andsaid interpretation is based on said routing parameters derived from theposition of the switching element.

These arrangements enable the same type of switching element to be usedin the different stages of a switching network and a single set ofrouting information to be employed in a cell and nevertheless differentmodes of transferring the cell to be used in the different stages of theswitching network, which provides great flexibility in the use ofdifferent routing modes to transfer a cell across the switching networkaccording to a variety of possible transfer sequences.

In a particularly advantageous application mode, the switching elementsof at least certain stages of the network include means for interpretingrouting information contained in a routing tag of a cell, which includesa routing control code (RCC) defining the required sequence fortransferring the cell across the switching network, an output portaddress (RCA), for a point-to-point routing and/or a multicast treeinternal reference number (IRN) for a point-to-multipoint routing.

The switching elements considered, interpreting said routing controlcode on the basis of said routing parameters derived from the positionof the switching element are designed to select as a result a routingmode which can be, among others, a point-to-point routing or apoint-to-multipoint routing.

The invention covers the case in which the switching elements of allstages are symmetrical, having the same number of inlets and outlets,and in which the switching network is consequently symmetrical, havingthe same number of input ports and output ports.

According to another characteristic of the invention, the switchingelements of at least one stage can be asymmetric, each implementing anexpansion of the traffic entering the stage, reducing the cell trafficload of the outlets of these switching elements with respect to theirinlets.

Such arrangements can be used to reduce the load of the outlets of theswitching elements and therefore the retention of the cells or theirloss in the switching elements or the corresponding buffer memoryrequirements in these switching elements.

Conversely, the switching elements of at least one stage can beasymmetric, each implementing a concentration of traffic leaving thestage, increasing the cell traffic load of the outlets of theseswitching elements with respect to their inlets.

Each of these two types of use of asymmetric switching elements in atleast one stage enable asymmetric switching networks to be constructedin which the number of input ports and output ports are different, inthe first case to distribute the traffic over a greater number of outputports and in the second case to concentrate the traffic onto a smallernumber of output ports.

In addition, stages which are asymmetric but in different directions canbe combined in the same switching network. In particular, it is evenpossible to construct a symmetrical switching network having the samenumber of input ports and output ports in which at least one of thefirst stages is asymmetric and implements a traffic expansion and atleast one of the last stages is asymmetric and implements a trafficconcentration which compensates for the previous expansion. This thenleads to a reduction in the traffic load on the internal links of theswitching network between these two asymmetric stages with theadvantages mentioned above.

Another object of the invention is a switching network in which theswitching elements of at least certain stages route cells belonging totwo opposing traffic streams, and in which, in each of these switchingelements called bidirectional switching elements, the inlets are dividedinto two sets of inlets and the outlets into two sets of outlets, onetraffic stream normally being routed from a first set of inlets to afirst set of outlets and the other traffic stream from a second set ofinlets to a second set of outlets; the interpretation of the routinginformation in the switching element also takes account of the trafficstream to which it relates to determine whether the routing should be"normal", that is to the associated set of outlets (same traffic stream)or "reflected", that is to the other set of outlets (opposite trafficstream).

The invention also extends however to the case in which the switchingelements of all the stages of the switching network are unidirectional,routing cells belonging to a single traffic stream routed from theinlets of each of these switching elements to their outlets.

According to one embodiment of the invention, the switching networkcontains at least three unidirectional stages, each switching element ofa stage other than the last being connected by one or more links to eachswitching element of the following stage and each switching element ofone stage other than the first being connected by one or more links toeach switching element of the preceding stage.

According to another embodiment of the invention, the switching networkcontains at least one inlet selection unit and at least one outletselection unit, each formed of switching elements arranged in at leasttwo stages and in each of which each switching element of a stage otherthan the last is connected by one or more links to each switchingelement of the following stage and each switching element of a stageother than the first is connected by one or more links to each switchingelement of the preceding stage, the inlet selection units being disposedin tandem with the outlet selection units, the input ports beingconnected to the inlets of the inlet selection units and the outputports to the outlets of the outlet selection units.

In this last embodiment, a single inlet selection unit can be connecteddirectly to a single outlet selection unit, by cross connection betweenthe outlets of the first and the inlets of the second.

In the case of several inlet and outlet selection units, according tothe invention, the switching network can also include selection unitscalled selection planes each connecting inlet connection unit outlets tooutlet selection unit inlets.

According to another characteristic of the invention, in the switchingelements of at least one stage, one of said groups of outlets of aswitching element contains all the outlets of the switching element, inthe case of a unidirectional switching element, or all the outlets ofone of the two sets of outlets for a given transfer direction, in thecase of a bidirectional switching element, for a general distribution ofthe incoming traffic over all the outlets of this stage in the incomingtransfer direction.

According to another embodiment of the invention, the switching networkis configured as an extensible folded network, having at least twostages at least one of which is bidirectional, the input ports beingconnected to the inlets of said first set of inlets of the switchingelements of a first stage and the output ports being connected to theoutlets of said second set of outlets of these same switching elementsof the first stage, when this is bidirectional, the last stage beingcomposed of unidirectional switching elements which route an incomingtraffic stream to the switching elements of the preceding stage, therebyimplementing a traffic reflection function.

When the first stage is not composed of bidirectional switchingelements, but of two counterpart sets of unidirectional switchingelements (one for each direction of transfer), the input ports areconnected to the inlets of the incoming switching elements and theoutput ports to the outlets of the outgoing switching elements.

According to this last embodiment, the folded switching networkcomprises at least two stages at least one of which is bidirectional andeach switching element of a stage other than the last is connected byone or more links to each switching element of the following stage andeach switching element of a stage other than the first is connected byone or more links to each switching element of the preceding stage.

According to an alternative to this last embodiment, the foldedswitching network comprises at least three stages and at least the firsttwo stages consist of inlet and outlet selection units each formed fromswitching elements arranged in at least two stages and in each of whicheach switching element of one stage other than the last is connected byone or more links to each switching element of the following stage andeach switching element of one stage other than the first is connected byone or more links to each switching element of the preceding stage.

In this last case, to construct large capacity switching networks whichcan grow in terms of the number of stages, said inlet and outletselection units can be interconnected by a number of selection unitscalled folded selection planes, each comprising an arrangement of one ormore stages according to the required capacity.

These different types of folded switching network having at least onebidirectional stage offer the advantageous property of being extensiblein terms of the number of stages, according to the required capacity interms of the number of network ports, without requiring alterations inthe wiring between stages. Any bidirectional stage can temporarily formthe last equipped stage of an intermediate configuration through itsability to "reflect" traffic from the incoming transfer direction to theoutgoing transfer direction.

In the last embodiments envisaged, advantageously, the first stage orstages of the switching network effect a general distribution of theincoming traffic over the set of possible paths, that is over all thelinks, between these first stages, thereby implementing a distributionof the received cells over the input ports on a multiplicity of paths.In a unidirectional switching element of such a stage, the singlerouting group therefore comprises all the outlets of the switchingelement; in a bidirectional switching element of such a stage, the setof outlets in the incoming transfer direction forms the single routinggroup through which the incoming traffic is distributed. To implementsuch a distribution of incoming traffic, according to the invention,each cell must be capable of selecting any of the available outlets insuch a distribution routing group.

Advantageously, then, the switching elements of one or more of the firststages of the switching network are constructed so that, when therouting data specifies a point-to-point transfer and/or apoint-to-multipoint transfer, and taking into account said positiondata, the incoming traffic is evenly distributed in the first stage orstages.

Advantageously also, the selection of one of the outlets of a group isperformed in a way which balances the cell load over the differentoutlets of this group.

Advantageously also, said selection performed in a way to balance thecell load over the different outlets of this group is based on a quasior pseudo-random distribution process intended to achieve adecorrelation between the distribution of cells over the inlets and thedistribution of cells over the outlets of the switching element.

The quasi or pseudo-random distribution is performed on selection of anoutlet from the different outlets belonging to the selected routinggroup. This can take place before the identities of cells are stored inqueues which are then individually assigned to the outlets. In addition,the two arrangements described above, load balancing and randomdistribution, can advantageously be combined.

Multiple path, self-routing switching networks according to theinvention also present the following characteristics:

- The combined use of a multiplicity of paths to transfer the differentcells of a call to the output port or ports concerned and switchingelements storing the cells for an undefined time, results in these cellsbeing routed to the output port or ports with a variable transfer timelikely to alter the order of successive cells. This characteristicinvolves the introduction of circuits to re-establish the order of cellsat each outlet port of the switching network.

- The distribution of incoming cell traffic over a multiplicity ofpossible paths in the first distribution stages leads to thecharacteristic property that the bit rate of internal connections ofsuch switching networks is no longer dependent on the bit rate of theexternal transmission connections connected to it, or on the bit rate ofservices transmitted over these external connections. The principle ofdistribution by a multiplicity of paths within the network enables theincoming flow of cells from a high bit rate external connection to bedistributed over several input ports of the lower bit rate switchingnetwork; for example, a 2.4 Gbit/s external connection can be connectedto 16×150 Mbit/s input ports. After transfer of the cells in theswitching network over all possible paths, the cells requiring anoutgoing external connection at the same bit rate of 2.4 Gbit/s arerouted to a group of 16×150 Mbit/s output ports in which the cell orderis re-established and asynchronous multiplexing performed over the 2.4Gbit/s outgoing connection.

Similar reasoning shows that a service which would require a cell bitrate equivalent to 200 Mbit/s can be transferred through the switchingnetwork over a multiplicity of paths, each corresponding to a 150 Mbit/sinternal connection.

- The distribution of the incoming traffic in the first distributionstages also has the characteristic consequence of implementing anaveraging of the load on the external connections over the switchingelements of the internal stages of the switching network. It is thenpossible, for example, to equip a variable number of selection planesaccording to the average traffic load over all the external connectionsof the most heavily loaded selection unit in terms of traffic.

- With respect to point-to-multipoint transfers, according to predefinedmulticast trees, the multiplicity of possible paths to transfer a cellacross the multiple path, self-routing switching network requires acharacteristic organisation of the content of the multicast treememories of the switching elements of the different stages. According tothe invention, it is possible to define corresponding branch points sothat no unnecessary copy is generated in any stage, which avoidsinternal overloading on the internal links between stages.

The above-mentioned and other objects and features of the invention willbecome more apparent and the invention itself will be best understood byreferring to the following description of an embodiment taken inconjunction with the accompanying drawings wherein:

FIG. 1 is a known diagram of the circuit of a switching element ISEemployed in the switching network of this invention,

FIG. 2 represents the format of a cell, designed for the implementationof this invention,

FIG. 3 is a diagram of a method of applying the switching element inFIG. 1, for routing cells in two opposite directions,

FIG. 3b is a detailed diagram of the subcell buffer management logicSBML in FIG. 1,

FIG. 4 is a diagram of the routing logic RL according to the invention,applicable in the switching element in FIG. 1, enabling it to be used inaccordance with FIG. 3,

FIG. 4b is a detailed diagram of the cell output queuing managementlogic COQML in FIG. 1,

FIG. 5 is a symmetrical unidirectional switching network according tothe invention,

FIG. 6 is a four-stage symmetrical unidirectional switching networkarranged as two back-to-back selection units each having two stages,

FIG. 7 is a folded symmetrical switching network corresponding to thatin FIG. 6,

FIG. 8 is an asymmetric unidirectional switching network with two timesthree stages,

FIG. 9 is a three stage asymmetric bidirectional switching networkcorresponding to the preceding network,

FIG. 10 is an asymmetric bidirectional switching network with a numberof two-stage selection units,

FIG. 11 is a symmetrical unidirectional switching network with a numberof two-stage selection units interconnected by a number of three-stageselection planes, and

FIG. 12 is a folded symmetrical switching network corresponding to thatin FIG. 11.

In the figures, to simplify matters, various connections are representedas single wires, although they can incorporate a plurality of suchwires. In addition, the figures do not represent all the controlcircuits, their implementation obviously being derived, for thoseskilled in the art, from the content of the description.

The switching element represented in FIG. 1 with X inlets I1/IX and Youtlets O1/OY (X and Y not being equal to 1 at the same time) isconstructed to switch digital signals grouped in cells or packets offixed or variable length. Such a cell, represented in FIG. 2, is forexample constructed from a series of successive subcells, comprising afirst subcell FSC, an intermediate subcell ISC and a last subcell LSC,all equal in length, for example 162 bits, or 2 bits and 20 eight bitcharacters. Each of these subcells contains a subcell control header SCHand a data block DB1 - DBs, the first subcell FSC containing in additiona cell control header CCH which, for example, contains routinginformation enabling the switching element to determine to whichgroup(s) of outlets RG1/RGY all the successive subcells belonging to thesame cell must be successively transferred, this transfer taking placeon the same outlet or outlets. In this description, the subcell controlheader SCH is assumed to have an explicit binary value 11, 00 or 01indicating that the subcell is respectively the first subcell FSC, anintermediate subcell ISC or the last subcell LSC of the cell.

The cell control header CCH itself contains three parts, a routingcontrol code RCC, a destination indication in the form of a networkoutput address RCA and a multicast tree internal reference number IRN.

The routing control code RCC, which can comprise five bits, containsrouting mode data denoting a point-to-point routing mode or a broadcastor multicast routing mode, or any other required routing mode, certainof which will be explained subsequently. If, for a switching element,the routing control code RCC denotes the point-to-point routing mode,analysis of the network output address RCA identifies the selected groupof outlets. If the routing control code RCC denotes the broadcast ormulticast routing mode, the multicast tree internal reference number IRNis used to read a memory which provides the identities of the groups ofoutlets corresponding to the branch to be performed for this tree in theswitching element.

The network output address RCA which will comprise up to 14 bits, forexample, is the identity of the output port of the switching network (ora group of output ports) to which the received cell is to be addressed.When selective routing is performed by more than one stage of theswitching network only part of this destination data is required in eachof the switching elements to route the cell.

The internal reference number IRN which will also comprise for example14 bits, is a number used in the switching network to identify themulticast tree according to which an incoming cell is to be transferredto a certain number of given output ports. It is interesting to notethat according to the invention, a multicast tree in a self-routing,multiple path network is not a point-to-multipoint connection, because,being independent of the input port, it is characterised only by the setof destination output ports; in addition, in such a multiple pathnetwork, it corresponds to a multiplicity of potentialpoint-to-multipoint paths between the set of input ports and the set ofdestination output ports of the multicast tree in question. In fact, agiven multicast tree internal reference number IRN is not necessarilyspecific to a single call, but may be used by all the calls from anyinput ports needing to transfer each cell to the set of destinationoutput ports of this multicast tree.

FIG. 3 now represents, for reasons of drafting convenience, a method ofusing the switching element ISE in FIG. 1 in the case of bidirectionalrouting, with a reflection facility, which will be explainedsubsequently with reference to FIGS. 7, 9, 10 and 12.

The switching element ISE, in the example in question, comprises 32inlets I1 to I32 and 32 outlets O1 to O32. The inlets I1 to I32 aredivided into two sets of inlets I1 to I16 and I17 to I32. The outletsare divided into two sets of outlets O1 to O16 and O17 to O32.Internally, other than in the reflection situation, the switchingelement is constructed to provide for normal left to right routing frominlets I1 to I16 to outlets O1 to O16, and, in parallel, but from rightto left because of the external wiring method, inlets I17 to I32 tooutlets O17 to O32. In the reflection situation, the switching elementprovides for the routing of inlets I1 to I16 to outlets O17 to O32, orinlets I17 to I32 to outlets O1 to O16. In such a switching element, theassignment of the inlets to the routing directions is predetermined. Itmay be indicated by a bit IO attached to each inlet and which indicateswhether it belongs to an "incoming" direction (I1 to I16, for example,routing traffic normally intended for the set of outlets O1 to O16) orthe opposite "outgoing" direction (I17 to I32, in the same example,routing traffic normally intended for the set of outlets O17 to O32.

The set of 16 outlets in each direction can be, for example, dividedinto a maximum of eight groups of at least two outlets and the routingof any cell to the outlets of one of the groups simply requiresidentification, by an 8-bit word (one bit per group) of the group orgroups to which the cell is to be forwarded, it being understood thatthe cell is forwarded over a single outlet of each group thusidentified.

Referring to FIG. 1, inlets I1/IX of the switching element representedtherein are connected to the respective data inputs of a multiplexcircuit MX through the intermediary of the cascade connection ofrespective serial/parallel converter circuits SPR1/SPRX and respectivelatches IL1/ILX. The data output CI of multiplexer MX is coupled to thedata input, also CI, of a subcell buffer RAM BM, while the selectioninput XI of the multiplexer MX is controlled by an input clock circuitXC capable of connecting successively each of the X inputs of themultiplexer to the output of multiplexer CI, during a subcell period.Such a subcell period is the time interval in which a subcell isreceived in a serial/parallel converter circuit SPR1/SPRX.

The buffer memory BM is totally shared and its data output is connectedto the data input of a demultiplexer DX the Y data outputs of which arecoupled to respective outlets O1/OY through the intermediary ofrespective parallel/serial converter circuits PSR1/PSRY. The selectioninput YJ of demultiplexer DX is controlled by an output clock circuit YCcapable of connecting successively the input of the multiplexer to the Ydemultiplexer outputs during a subcell period.

Note that, for subcells having a length of 162 bits and for the same bitrate of 50 Mbit/s at the inputs and outputs, a subcell period is equalto:

    162/50=3.24 μm.

More precisely, when, for example, the switching element has X=32 inletsand Y=32 outlets, 32 write operations and 32 read operations, or 64operations, must be performed in the buffer memory BM during a singleoperations must be performed in:

    3.24/64=50.62 ns.

In addition, when for example X=16 and Y=32, 48 operations must beperformed during the same subcell period. This means that each of theseoperations must be performed in:

    3.24/48=67.50 ns.

The buffer memory BM is divided into C, 512 for example, subcell buffermemory locations, each capable of storing one subcell, for example of162 bits; it has an address input AC, and a read/write selection inputRW, respectively coupled to the outputs of the same names of a subcellbuffer management logic SBML.

The switching element also comprises a subcell logic SL and a routinglogic RL, which are both coupled to the data output CI of themultiplexer MX.

The subcell logic SL is mainly a detector designed to detect and verifythe subcell control header SCH of each subcell and to provide activeoutput signals LS, FO or NF, according to whether the subcell isrespectively the last subcell LSC, a first subcell FSC or is not a firstsubcell.

The routing logic RL analyses the routing information in the cellcontrol header CCH of each first subcell FSC of a cell and providesactive output signals RMD and RC, according to the routing information.More particularly, signal RMD provides the identity of one or moreselected groups of outlets over which the subcells of the cell are to betransferred while signal RC indicates the number of the selected outletgroups, i.e. one for a point-to-point transfer and a value higher thanone for a point-to-multipoint transfer. The type of routing informationand the corresponding analysis process performed by the routing logic RLto generate output signals RMD and RC depends on the routing modeemployed for the cell. The cell control header CCH can, for example,contain Y bits of routing information, each of these bits correspondingto a group of outlets over which the cell is to be transferred. Theoutput cell queue management logic COQML shown in detail in FIG. 4b issimultaneously performs cell queue management and outlet selectionfunctions, by storing the first write-in subcell address WISA in anappropriate queue BQ1/BQZ, according to the routing mode and data RMDsupplied by the routing logic RL, and by transmitting the first read-outsubcell address FSAO to the logic SBML, at the same time as the identityof the selected outlet YS.

The subcell buffer management logic SBML is coupled to the previouslymentioned outputs LS, NF of the logic SL, RC of the logic RL, XI of theinput clock circuit XC, FSAO of the cell output queueing managementlogic COQML, and YJ of the output clock circuit YC. It manages the useof the locations of the buffer memory BM, by providing the addresses offree locations, rendering them busy when they are in use and releasingthem when they are no longer in use. Under the control of signalsapplied to its inputs, it also controls, via the read/write selectionsignal RW, read and write operations in the buffer memory BM at the sametime forming linked lists linking the subcell buffer addresses of aparticular cell. This is necessary because the subcells of a particularcell are stored in uncorrelated locations of the buffer memory BM,whereas they must be routed over the same selected outlet or outletsO1/OY, in the same order, without interruption, as they arrived at oneof the inlets I1/IX.

There now follows a brief description of the operation of the switchingelement in question. When a subcell of a variable length cell, such asrepresented in FIG. 2, appears at one of the inlets I1/IX, I1 forexample, of the switching element, it is received by the correspondingserial/parallel converter circuit SPR1. Supplied by this convertercircuit SPR1, the parallel version of the subcell is transferred to thecorresponding interlock circuit IL1, through which it is sent to themultiplexer MX. Under the control of the clock signal XI provided at theinput of the same name by the input clock circuit XC, the subcell, at acertain moment, corresponding to this inlet I1, is sent to the datainput CI of the buffer memory BM, and to the subcell logic SL and therouting logic RL. It is then determined whether the subcell is a firstsubcell FSC, a last subcell LSC, or is not a first subcell, and forwhich group or groups of outlets RG1/RGY this subcell--and followingsubcells belonging to the same cell--must be respectively transferred.The resulting output signals LS, NF and RC are applied to the subcellbuffer management logic SBML and the output signal RMD to the celloutput queueing management logic COQML.

Under the control of clock signal XI, the logic SBML provides theaddress of a free buffer location, WISA for example, to the addressinput AC of the buffer memory BM, in consequence of which the subcellpresent at the data input CI of the buffer memory BM is stored in thememory location having the address WISA. This address WISA is renderedbusy and is added to the linked list of addresses of all subcellsalready received from the same cell (in this case the signals NF, LS, RCand RMD are used). In this list, the addresses are in the same order asthat of the subcells of the cell.

During a read operation, under the control of clock signal YJ providedat the input of the same name by the output clock circuit YC, theaddress of a subcell, ROSA for example, is provided at the address inputAC of the buffer memory BM and the subcell in the corresponding memorylocation is read and transferred to the data output of the buffer memoryBM. From there, it is sent, through the intermediary of thedemultiplexer DX to the outlet or one of the outlets initially indicatedby signal YS of the cell output queueing management logic COQML.

Refer now to FIG. 3b is, which represents the subcell buffer managementlogic SBML in FIG. 1 in greater detail.

As already stated, this subcell buffer management logic has inputs LS,NF, RC,XI, YJ, FSAO and YS, and outputs AC, L, RW and FSAI. It comprisesa free memory location management circuit FMLMC, a subcell link memorySLM, an input subcell pointer memory ISPM and an output subcell pointermemory OSPM.

The FMLMC circuit of the SBML logic consists of a free location queuememory FQ which is, for example, a FIFO memory storing the addresses ofall the free locations of the buffer memory BM. The FMLMC circuit has aninput ROSA, an output WISA and control terminals QC and RW.

The subcell link memory SLM comprises C memory locations correspondingto the C buffer memory locations of the subcell buffer memory BM andstores, for each of them:

- the link address to the next subcell (NCB),

- the number of subcell copies which must be read (NC),

- a flag indicating the last subcell of the cell (L).

The subcell link memory field SLM is associated with a downcounter DC,such that the value NC is decremented by unity each time the memory SLMis read; then, the new value is stored instead of the previous value.Clearly, when the new value reaches zero, all subcell copies have beenread and the downcounter DC generates a signal QC used to store theaddress of the subcell read (ROSA), which becomes free, in the freememory location management circuit FMLMC.

The input subcell pointer memory has X locations corresponding to the Xinlets and it operates in synchronism with the input clock signals XIdefining the time division multiplex operation of the X inlets. For eachinlet, it stores:

- the buffer address of the last subcell received (LCB),

- the number of subcell copies which must be read later (LC),

- a flag indicating the last subcell of the cell (B).

The output subcell pointer memory has Y locations corresponding to theYK outlets and it operates in synchronism with the output clock signalsYJ defining the time division multiplex operation of the Y outlets. Foreach inlet, it stores the address of the location of the next cellwaiting to be transmitted to the outlet in question (WCB).

The write control circuit provides the various circuits with theappropriate control signals corresponding to alternate operation of theSBML circuits associated with the alternate read and write operations inthe buffer memory BM, as a result of the interleaved clock signalsrelating to the inlets (XI) and the outlets (YJ). In accordance withthis, the resulting signal RW is active during each write operation inthe buffer memory BM, for the write-in of a subcell, and inactive duringa read operation of the buffer memory BM for the read-out of a subcell.

The following description characterises the operation accomplished bythese subcell buffer management logic functions during a write or readphase and for each of the three types of subcell of a cell: firstsubcell FSC, intermediate subcell ISC and last subcell LSC.

Consider first the write phase in the buffer memory BM, in the case of afirst subcell FSC. In such a case, the signal FO is provided and themanagement logic SBML receives from the SL logic and the RL logic:

- NF=0, to indicate a first subcell,

- LS=0 to indicate that it is not a last subcell,

- RC=2, assuming for example the case of a point-to-multipoint transferover two groups of outlets.

The signal RW being active, a write-in subcell address is provided bythe management circuit FMLMC, which is the selected free buffer locationin which the received subcell is stored. The address WISA is also storedin the input subcell pointer memory ISPM for the inlet XI, in order tostore it as the last subcell address received, with a view to the nextcycle relating to the same inlet. In addition, the address WISA is alsoprovided to the COQML logic which stores it as a reference identity ofthis new received cell, because this cell receives the signal FO withthe value 1.

With respect to the subcell link memory SLM, because it is a firstsubcell FSC (NF=0), the address WISA is not stored in the NCB field,since this new subcell does not need to be linked with the last subcellof the previous cell. In addition, the other data fields are used forthis previous subcell by selecting its address which is supplied by theLCB field of the input subcell pointer memory ISPM and by storing LC andB from the input subcell pointer memory ISPM in fields NC and L of thesublink memory SLM respectively. The control signals RC and LS arestored respectively in fields LC and B of the ISPM memory for inlet XI.

In the case of an intermediate subcell, the signal FO is inactive andthe subcell buffer management logic SBML receives from the subcell logicSL and the routing logic RL the signals:

- NF=1,

- LS=0,

- the RC signal is not used with NF=1.

As before, signal RW is active and another address WISA is supplied bythe management circuit FMLMC, the memory location address which is used:

- to address the buffer memory BM and write in it the intermediatesubcell ISC,

- to be stored in the LCB field of the ISPM pointer memory as the newlyreceived last subcell address of the cell,

- to be stored in the NCB field of the SLM memory addressed by thecontent of the LCB field of the ISPM memory, in order to write in itthat this new address WISA is the address of the next subcell linkedwith the previous subcell which is in fact the selected memory locationin the SLM memory.

Simultaneously, the data of fields LC and B of the ISPM memory aretransferred into fields NC and L of the SLM memory, before B is replacedin the ISPM memory with a new value from signal LS.

In the case of a last subcell LSC, signal FO is inactive and the subcellbuffer management logic receives from the subcell logic SL and routinglogic RL:

- NF=1,

- LS=1,

- while RC is not used since NF=1.

Again signal RW is active and another address WISA is provided by theFMLMC circuit and the corresponding buffer location address is used inthe buffer memory BM, and the ISPM and SLM memories exactly as in theprevious case of storing an intermediate subcell ISC.

Simultaneously, the values LC and B of the ISPM memory are transferredinto fields NC and L of the SLM memory before B is replaced in the ISPMmemory by the new value from signal LS, consequently indicating that,now, the last subcell of a cell has just been received.

However, as emphasised in the description relating to the storing of afirst subcell SFC, during the next cycle relative to inlet XI, thevalues LC and B=1 will be transferred into fields NC and L of the SLMmemory at the address of the previous cell (the last) provided by theLCB field of the ISPM memory.

Consider now the read phase of the buffer memory BM during which signalRW is inactive. Consideration will first be given particularly to thecase of reading a first subcell FSC.

It must be assumed that, when the first subcell is sent, the content WCBof the output subcell pointer memory OSPM of the outlet considered YXhas been initialised with the address of the first subcell of the cellto be transmitted. This will appear further on, when the last subcell ofthe cell is read.

The output subcell pointer memory OSPM then provides the address of theoutput subcell to be read which is used:

- to address the buffer memory BM for reading the corresponding firstsubcell FSC,

- selecting the SLM memory in read mode, which provides:

- an indication NCB which is transferred to the OSPM memory to be storedas a new address WBC, with a view to the next cycle relating to outletYJ,

- an indication NC which is decremented by unity and re-stored as a newindication NC if it is other than zero; if the value zero is obtained,which means that the required number of read-outs of this subcell(providing the required number of copies of it) has been performed, theDC circuit generates a signal QC enabling the FMLMC circuit to recordthat the read-out subcell address ROSA buffer memory location can bereleased and included in the set of free buffer locations;

- a value L which is zero since it is not the last cell and initiatesthe previously mentioned transfer of the value NCB from the SLM memoryto the WCB field of the OSPM memory, via the multiplexer SO.

In the case of an intermediate cell ISC, the same operations take placein the OSPM and SLM memories and in the FMLMC circuit as for reading afirst subcell FSC.

In the case of a last subcell LSC, the OSPM memory again provides theROSA address of the subcell to be sent, a last subcell LSC in thepresent case, which is used:

- to address the buffer memory BM for reading the last subcell,

- selecting the SLM memory in read mode, which provides:

- a value NC which is decremented and treated exactly as in the othersubcell read situations,

- a value L, now equal to one, indicating that a last subcell LSC ispresent, which in this particular case prevents the transfer of thevalue NCB from the SLM memory to the WCB location of the OSPM memory,since there is no link to a subsequent subcell provided by the value NCBof the SLM memory in the case of a last subcell LSC; instead, L=1 isprovided to the COQML logic to indicate that the outlet in question YZis available for sending a subsequent cell, in the next cycle, since alast subcell of a cell is currently being transmitted.

Then, after selection by the COQML logic of the appropriate cell whichis to be transmitted to the outlet YJ in question, the COQML logicinitialises the value WBC in the OSPM memory in respect of outlet YJ, bywriting in it the buffer location address of the first subcell FSAO ofthe next cell selected, before the next cycle concerning outlet YJ.Because this initialisation process is not implemented during the clockperiod YJ of the last subcell LSC, an asynchronous access to the OSPMmemory is used, by means of the output address YS provided by the COQMLlogic.

While this embodiment of the subcell buffer management logic SBML hasbeen described to illustrate the subcell buffer management principlesemployed for the transfer of cells consisting of subcells between anyinlet and any outlet or outlets of the switching element, otherembodiments of the functions of this management logic SBML, for examplewith respect to the free memory location management circuit FMLMC, arealso included in types of switching element in accordance with thisinvention.

FIG. 4 represents an embodiment of the routing logic RL constructed foruse in the switching element ISE in FIG. 1, and also providing forbidirectional operation as illustrated in FIG. 3.

The circuits in FIG. 4 receive, in a register IR, the cell controlheader CCH mentioned in FIG. 1, and output the information marking thecontrol connection RMD which provides to the cell management and outletselection logic the information specifying the selected routing mode(RS, MC, DI, ES, PH), and the routing data (RG, PO).

The routing mode information is as follows:

- a "group" mode signal RS, which is present when the cell is to beforwarded to one of the outlets of a group of outlets, in the case ofpoint-to-point routing,

- a "multicast" mode signal MC, which is present when the cell is to berouted to one of the outlets of each of several groups of outlets, inthe case of point-to-multipoint routing,

- a "distribution" mode signal DI, which is present when the cell is tobe forwarded to one of the outlets of a set of outlets in the senseexplained with reference to FIG. 3, in the case of a bidirectionalswitching element, or to one of all the outlets of the switchingelement, in the case of a unidirectional switching element, therebyimplementing a general distribution, to achieve an even distribution ofthe cells received by the switching network,

- a "service" mode signal ES, which indicates that the cell received isintended for a particular control outlet,

- a "directed transfer" mode signal PH which indicates that the cell isto be forwarded to a predetermined outlet, for test reasons, forexample.

The routing data of the RMD connection comprises:

- group identity signals GL which identify the group or groups to anoutlet of which the received cell is to be forwarded, for routing modesRS and MC,

- individual output identity signals PO used with routing mode PH.

The circuits in FIG. 4 also receive, according to the inlet on which areceived cell arrived, an incoming direction indication IO which is forexample provided by the receiving circuit supplying the cell inquestion, on the input multiplexer in FIG. 1, specifying the incomingdirection concerned, in the sense mentioned with reference to FIG. 3.

The circuits in FIG. 4 comprise the following components:

- the register IR already mentioned, to receive the cell control headerCCH of each cell received, which comprises, as indicated, theinformation RCC, RCA and IRN,

- a routing control code translation memory RCCTM, storing 32 words of16 bits, called routing parameters, each comprising a 3-bit routing modecode MT, a reflection flag or bit EF, a 6-bit "incoming" routing groupfield RPI and a 6-bit "outgoing" routing group field RPO,

- a multicast memory MCM, storing a plurality of 8-bit mask words MSK,one bit for each group of outlets, each identifying the differentrouting groups to which a copy is to be sent,

- a routing mode decoder TD, decoding the routing mode code MT andconsequently providing one of the five mode signals mentionedpreviously,

- a direction selector RD, selecting either the "incoming" routing groupfield RPI or the "outgoing" routing group field RPO of the routingcontrol translation memory RCCTM, according to the reflection flag EFand the incoming direction flag IO,

- an outlet group selector MS having two parallel 8-bit inputs, whichprovides the group identity signals RG, also of 8 bits, each bitcorresponding to a separate group from the eight possible routinggroups,

- a 14-bit shift register SR having a five conductor output PO; if therouting method is the "physical" method PH, this output identifies theoutlet to which the received cell is to be routed,

- a routing group decoder GD,

- an exclusive OR-gate XOR, and

- two AND-gates, AN1 and AN2.

The routing logic circuits in FIG. 4 operate as described below, whenthe header of a received cell is present on the input multiplexer(FIG. 1) the cell control header CCH of which is sent to the registerIR, while the IO bit indicates the incoming routing direction. Asindicated above, a clock times the operation of the circuitsappropriately in accordance with the current state of the art.

The routing control code RCC, characteristic of a transfer sequenceacross the switching network, does not directly indicate the routingmode to be applied to the switching element in question. This routingmode depends on the type of switching network and the position of theswitching element in the network.

The routing control code, to be interpreted, is used as a read addressin the routing control code translation memory RCCTM, for the routingparameters comprising the components MT, EF, RPI and RPO defined above.

The routing method code RT is decoded by the routing method decoder TDwhich consequently provides one of the mode signals RS, MC, ES, DI orPH.

The incoming direction flag IO is applied to one of the inputs of theexclusive OR-gate XOR while the reflection flag EF is applied to itsother input. The output of the XOR gate provides the control signal ofthe outgoing direction selector RD. The outgoing direction selectorselects either the "incoming" routing group field RPI or the "outgoing"routing group field RPO, specifying, for each set of outlets, a specificpart of the destination address RCA which is to provide the identity ofa routing group to one of the outlets of which the received cell is tobe forwarded. Each of these fields include a 4-bit position flag POS anda 2-bit dimension flag RGS. The position flag POS controls the shiftregister SR so that the RCA information is shifted in it and part of thethree bits that it contains come into the three lefthand stages, on thefigure, of this register SR, or part of the five bits it contains comeinto the five lefthand stages, on the figure, of the register SR. Thedimension flag RGS indicates how many of the three bits mentioned firstmust be used to define the identity of a routing group. Thus, thelefthand bit of these three bits is transmitted directly from the shiftregister SR to the group number decoder GD, the next bit is transmittedby the AND-gate AN1 controlled by one of the RGS signals and a third bitby the AND-gate AN2 controlled by the other RGS signal. The group numberdecoder GD provides an 8-bit word which forms the identity of a routinggroup, applied to the selector MS. In this word, only one bit is at one,for example, all the others being at 0. Simultaneously, the 14-bitmulticast tree internal reference number IRN is applied by register IRto the multicast memory MCM, where it serves as the address for readingan 8-bit mask word MSK. As indicated before, this mask word identifiesone or more routing groups in an 8-bit word, one or more of which are at1, and the others at 0. It, too, is applied to the selector MS.

If the mode signal provided by the decoder TD is the "group" mode signalRS, selector MS provides at its output a group identity signal RG whichis the signal provided by the decoder GD; in the case of the "multicast"mode signal MC, signal RG transmitted by selector MS is the signal MSK.

In addition, the five lefthand stages of the shift register SR, afterthe shift generated by the position flag POS, directly provide theidentity PO of an outlet to which the received cell is to be forwarded,in the case of the "physical" routing mode PH.

In the particular case of the "distribution" mode DI, no group ofoutlets needs to be identified, since there is only one group comprisingall the outlets of the set in question in the transfer direction inquestion.

In the case of the "service" mode ES, the outlet in question is knowndirectly, since the received cell is to be transmitted to a particularcontrol outlet represented in FIG. 1.

It can therefore be seen that the information in the routing controlcode translation memory RCCTM defines, in each switching element, theinterpretation that this switching element must make of the 32 possibletransfer sequences denoted by the routing control code RCC to determinethe routing mode to be applied according to the routing data in thereceived cell header. This is equivalent to combining the routinginformation from a cell, unchanged while the cell passes through theswitching elements of different stages of the switching network, withthe routing parameters of the switching element, derived from itsposition in the network, for example specific to each stage and leadingto a particular routing mode in each stage and for each routingsequence.

The information in the routing control code translation memory RCCTM issemi-permanent and can be written when each switching element is broughtinto service. However, the information in the multicast memory MCM mustbe modified during operation, to establish each multicast tree.

FIG. 4b is represents the general diagram of the cell output queueingmanagement logic COQML in FIG. 1.

When the decision to route a new received cell to an inlet of theswitching element is taken by the routing logic RL, the routing logicprovides the COQML logic with the routing mode information and theassociated routing data over the control connection RMD, this beingconfirmed by the control signal FO received from the SL circuit, whichindicates the presence of a first subcell FSC containing the informationfor routing the cell being received. In addition, simultaneously, thesubcell memory management logic SBML provides the COQML logic with theaddress WISA in the buffer memory BM, in which this first subcell FSChas been stored.

When an outlet YJ of the switching element transmits the last subcellLSC of a cell and is therefore going to become available to transmitanother cell, the subcell memory management logic SBML indicates a nextcell request by means of signal L then active, as explained previously,in the description of the SBML logic. Then, the COQML logic selects thenext cell to be transmitted to this outlet, by providing the SBML logicwith the address FSAO of the first subcell of the cell to be transmittedto outlet YJ, this last indication being notified by the outlet addressYS also supplied by the COQML logic to the SBML logic, in order to beable to perform this operation outside the synchronous clock time YJrelating to the outlet YJ.

The cell output queueing management logic COQML comprises the followingcircuits:

- queues BQ1/BQZ the respective inputs of which come from ademultiplexer BI and the respective outputs of which are linked to amultiplexer BO, and which provide the temporary storage for theidentities of cells awaiting output, on a first in/first out basis, saididentities being characterised for example by the addresses of the firstsubcell of each cell in the buffer memory,

- a queue input control logic QICL which receives the requests to queuecells,

- a queue output control logic which selects each next cell to betransmitted to one of the outlets of the switching element as soon as itbecomes available.

In addition to managing the temporary wait of cells to be transmitted,by storing their identities in queues, the COQML logic also controlsselection of an individual outlet in each selected routing group, giventhat for the point-to-point RS, point-to-multipoint MC and distributionDI routing modes, the routing logic RL identifies only the routinggroups to which a copy of the cell is to be transmitted, or all theoutlets in a direction in the DI mode.

In a first embodiment, this individual outlet selection function isperformed by a queue input control logic QICL, before the identity ofthe cell is queued. In this case, each queue BQ1/BQZ is directlyassociated with each of the Y outlets of the switching element.

Another equivalent embodiment consists in the same outlet selectionfunction being performed by the queue output control logic QOCL,therefore after the identity of the cell has been queued. In this secondcase, each queue BQ1/BQZ is associated with a routing group comprisingone or more outlets and not with an individual outlet of the switchingelement.

In either embodiment, the outlet selection device needed for routingmodes RS, MC and DI can be implemented in a known manner on the basis ofa cyclic distribution of cells to the outlets of a particular routinggroup, enabling the cell traffic load of the routing group to be evenlydistributed over each of its outlets. Another proposed solution is touse a quasi or pseudo-random signal generator to select an outlet foreach cell, which leads to the elimination, at least in large part, ofany correlation between the flow of cells over the inlets and theoutlets of each switching element.

In the case of the ES or PH modes, an outlet of the switching element isrespectively implicit or already selected and the role of the COQMLlogic is limited to the function of management of these queued cells foreach corresponding individual outlet.

There now follows, with reference to FIGS. 5 to 12, a number ofembodiments of the switching network according to the invention, basedon FIGS. 1 to 4, with respect to the specific characteristics of theswitching elements employed in the different stages of the switchingnetwork.

The properties of a switching network come from the properties of theswitching elements forming the network, as they are constructed,according to the invention through the semi-permanent routing parametersderived from the position of the switching elements and theconfiguration of the switching network, essentially consisting of thenumber of stages, the unidirectional or bidirectional nature of eachstage, the links between the switching elements and the input and outputport connection method.

The invention, as will be seen, applies in all switching networkconfigurations which are going to be described and in the numerousvariants which can easily be derived therefrom.

It is also worth indicating that in all switching networkconfigurations, it is generally desirable for reasons of standardisationand expandability, that the same type of switching element be used inall stages of the network. It can easily be verified that the switchingelement in FIGS. 1, 3 and 4 satisfies this requirement because it caneasily be initialised with specific routing parameters, for example bystage, for each cell transfer sequence across the switching network.

FIG. 5 represents a unidirectional, symmetrical switching network RC1,consisting of switching elements such as that in FIG. 1, arranged inthree stages comprising in the first stage switching elements TSi1 toTSiT, each with n inlets, in the central stage, switching elements Tso1to TSoT each with n outlets. In this way, the switching network has n=nTinput ports connected to the inlets of the switching elements of thefirst stage and n=nT output ports connected to the outlets of theswitching elements of the last stage. The cell traffic is routed fromthe input ports to the output ports passing through all the switchingelements in one direction; this is why the network is referred to asunidirectional. It is said to be symmetrical because the number ofoutlets is the same as the number of inlets. The T switching elements ofthe first stage have one or more (m) links to each of the k switchingelements of the central stage, or mxk outlets. The T switching elementsof the last stage have one or more (m) links from each of the centralstage switching elements, or mxk inlets. The switching elements of thecentral stage therefore have Txm inlets and Txm outlets. Taking thefigures previously quoted (FIG. 3, for example), the switching elementsof the three stages can be 32 inlet and 32 outlet switching elements,with Txm=kxm=32.

Since each of the switching elements of the central stage can reach allthe switching elements of the last stage, a cell reaching the switchingnetwork at any inlet port, of switching element TSi1, for example, canbe addressed to any of the central stage switching elements AS1 to ASk,whether the routing of this cell is point-to-point orpoint-to-multipoint. In such a network it can therefore be seen,according to the invention, that the outlets of the switching elementsof the first stage are arranged in a single group of outlets and that acell received by a switching element of the first stage, whether routingis point-to-point or point-to-multipoint, will be forwarded to aselected outlet from this single group of outlets. It is sufficient forthis (see description relative to FIG. 4) that the routing control codetranslation memory (RCCTM) in these switching elements TSi1 to TSiT,provide the "distribution" mode signal DI in exchange for routingcontrol code RCC information indicating that the cell is to bedistributed to any outlet to the next stage, for point-to-point orpoint-to-multipoint routing.

In other words, position data included in the switching elements of thefirst stage (implicitly represented by the routing parameters in therouting control code translation memory) will enable the routinginformation of the cell to be interpreted in this way.

However, with respect to the central stage switching elements, each ofthem has only one or more (m) links to each switching element of thelast stage. The routing depends on the identity of the destinationoutlet. A group of one or more (m) links is accessible for this purpose.Each switching element of the central stage will thus have T groups ofone or (m) outlets. With different position data, these switchingelements will interpret the same cell routing information, so as toselect the appropriate routing group, in the case of a point-to-pointrouting, or the appropriate groups in the case of a point-to-multipointrouting, involving outlets of several different switching elements ofthe last stage. According to the embodiment in FIG. 4, the routingcontrol code RCC considered above will be translated, in these switchingelements of the central stage, into a "group" mode signal RS, for apoint-to-point routing, or into an "MC" mode signal forpoint-to-multipoint routing, while the routing control address RCA, orthe internal reference number IRN, will be used to identify the group orgroups of outlets selected.

What applies for the switching elements of the central stage, relativeto the routing situations in question, also applies for the switchingelements of the last stage.

In the case where m=2, for example, the switching elements of thecentral stage have two links with each of the switching elements of thefirst and last stages. In this case, the switching elements of thecentral stage will have T groups of two outlets only one of which mustbe selected.

The number of switching elements of the central stage can, according toanother variant, be greater than that of the switching elements of thetwo end stages, ceteris paribus. This will reduce the traffic load onthe internal links of the switching network. Taking the previous example(m=2), the central stage could include 64 switching elements and,correlatively, the switching elements of the two m stages would have 128outlets or inlets.

It can also be envisaged that, for a given capacity of the network inFIG. 5, in terms of number of switching elements per stage and number oflink connections between them, certain input connections operating at atransmission speed greater than that practiced in the switching networkcould be coupled to several input ports over which the cells of thisexternal connection are distributed; these are then transferredindividually by the multiplicity of possible paths to the destinationoutput ports. By generalising, this can enable a switching network to beconstructed the switching and transmission speeds of which would belower than those of the external transmission connections which itserves. Of course, what has just been said on the subject of inputconnections applies symmetrically to the output connections in which thecells of several output ports are multiplexed to the outgoing externalconnection.

The symmetrical unidirectional switching network in FIG. 6 comprisesfour stages. The denotations of the switching elements of the two endstages are the same as in FIG. 5. The switching elements of the twocentral stages are respectively denoted ASi1 to ASik and ASo1 to ASok.

The switching elements of the first two stages form an inlet selectionunit USi, while the switching elements of the last two stages form anoutlet selection unit USo. These two selection units are coupled bylinks joining the counterpart outlets and inlets.

Everything explained with respect to the network in FIG. 5 still applieshere, considering that two counterpart switching elements of the twocentral stages form only one. However, from the control point of view,the switching elements ASi1 to ASik will advantageously be constructedto effect a distribution, whether the routing mode be point-to-point orpoint-to-multipoint. The switching elements ASo1 to ASok, from thecontrol point of view, will be treated in the same way as switchingelements AS1 to ASk in FIG. 5.

The switching network in FIG. 7 is similar to that in FIG. 6, butfolded, therefore bidirectional, merging the switching elements of theend stages TSi1 to TSiT and TSo1 to TSoT into switching elements of thefirst stage TS1 to TST, while the denotation of the switching elementsof the second stage in FIG. 5, AS1 to ASk is retained for the switchingelements of the second stage in FIG. 7.

The inlets of the switching elements of the first stage are sharedbetween the input ports and the output ports of the switching network(in equal parts for networks with no expansion/concentration function).The internal links are duplicated, comprising one or more connectionsfor each routing direction. The switching elements are bidirectional andperform the reflection function, either in the first stage or in thesecond stage.

In the routing of a cell from an inlet of switching element TS1 to oneor more outlets of another switching element TST, whether in the contextof point-to-point or point-to-multipoint routing, switching element TS1performs a distribution to all the switching elements of the next stage,while the switching element of the second stage which routes the cellapplies the "group" or "multicast" routing mode and the same applieswith respect to the switching element TST. In the case of transferring acell from an inlet of switching element TS1 to one or more outlets ofthe same switching element TS1, a transfer reflection function can beoperated directly in the first stage, that is in the bidirectionalswitching element TS1 which directly transfers the cell to thedestination outlet or outlets, instead of transferring it normally fordistribution to the next stage.

Everything which has been said concerning the network in FIG. 5therefore also applies to the network in FIG. 7, making the necessaryconversions, taking into account the superimposition of the two routingdirections of the traffic in the switching elements of these two stagesand execution of a reflection function in the switching elements of thefirst or second stage.

Referring to FIG. 3, the switching elements of the first stage comprise16 inlets and 16 outlets connected respectively to input ports and tooutput ports. They also comprise 16 inlets and 16 outlets connected to16/m switching elements of the second stage, where m is the number ofinternal links between two switching elements belonging respectively toeach of these two stages. If the first stage comprises 16 switchingelements (m=1), 16 inlets and 16 outlets of the switching elements ofthe second stage are respectively connected to the 16 switching elementsof the first stage by 16 bidirectional links each comprising a singleconnection in each routing direction. The traffic from these 16 inletsis then reflected to the 16 outlets. The other 16 inlets and outlets ofthe switching elements of the second stage are not used and areavailable for extending the network by adding a third stage. If thefirst stage comprises up to 32 switching elements, the 32 inlets and 32outlets of the switching elements of the second stage provide the 32two-connection links, one in each routing direction, which are necessaryto reach them.

The operating mode of the switching elements in processing the tworouting directions has already been explained with reference to FIGS. 3and 4.

Referring now to FIG. 8 which represents a switching network derivedfrom that in FIG. 5, but here obtained by juxtaposing two separate butcounterpart unidirectional switching networks stage by stage, eachallowing the transfer in a given direction, from N1 inlets on one sideto N2 outlets on the other side, or N2 inlets on this latter side to N1outlets on the former side. In fact, such a switching network cantypically be used to form an asymmetric assembly interconnecting N1bidirectional connections on one side to N2 bidirectional connections onthe other side, where N1 is greater than N2. The unidirectional networkof N1 to N2 therefore implements a traffic concentration function andthe other unidirectional network from N2 to N1 a traffic expansionfunction. Each of these unidirectional networks therefore differs fromthat in FIG. 1 only in the fact that it is asymmetric because of thepresence of at least one stage of asymmetric switching elements, that isswitching elements in which the number of inlets and outlets differs,for example 32×16 or 16×32. Apart from this configuration variant, therouting principles described for each stage of the network in FIG. 5 arestill applicable to the corresponding stages in each of these twoasymmetric unidirectional networks.

FIG. 9 represents an equivalent of the switching network in FIG. 8, in abidirectional configuration. In this case the asymmetric switchingnetwork interconnects the N1 input and output ports on one side to theN2 input and output ports on the other side. Assuming N1 is greater thanN2, such a network is applied typically to the concentration of N1relatively low traffic connections to N2 higher traffic connections.Cell transfers can therefore be performed between these two sets ofports N1 and N2, either unidirectionally, from an input port of the setN1 (or N2) to an output of the set N2 (or N1), or bidirectionallybetween an input and output port of assembly N1 and an input and outputport of assembly N2. In addition, the presence of at least onebidirectional stage also enables cells to be transferred between aninput port and an output port of the same set N1 (or N2), performing areflection function in a bidirectional stage. From the configurationpoint of view, the capacity of this network is similar to that of FIG.8; as in FIG. 8, at least one of the stages is asymmetric, so that theswitching network presents different numbers of input and output portsN1 and N2 on either side of the switching network.

The different transfer sequences are applied as follows:

- For an unreflected cell transfer between an input port on one side ofthe network (set N1 or N2) and an output port on the other side of thenetwork (set N2 or N1), the first stage distributes the incoming trafficover all the switching elements of the intermediate stage. Then, theintermediate stage forms a selective routing to the last stage bytransferring the cell to one or more groups of outlets leading to one ormore switching elements of the last stage. In the last stage, aselective routing enables the cell to be transferred to the destinationoutput port or ports.

- For a reflected transfer, between an input port and an output port ofthe same set N1 or N2, the reflection function can be implemented in theswitching element of the first stage if the ports are connected to thesame switching element and if it is bidirectional. Otherwise, theswitching element of the first stage distributes the cell to any one ofthe switching elements of the intermediate stage, which willadvantageously be bidirectional to enable this type of reflectedtransfer by selective routing to be performed to the switching elementor switching elements of the first stage. In the first stage, aselective routing enables the cell to be transferred to the destinationoutput port or ports.

FIG. 10 represents a possible extension of the switching network in FIG.9 by adding an additional selection stage. In addition, the first twoswitching element stages, on the side of the N1 input and output ports,consist of m two stage bidirectional routing selection units, eachsimilar, apart from their capacity, to the network in FIG. 7, theswitching elements also being denoted by the same references as in FIG.7.

Apart from the addition of a fourth stage in the organisation of thefirst two stages on the side of the set of N1 ports, the types oftransfer possible in such an asymmetric bidirectional switching networkcan easily be extrapolated from that in FIG. 9:

- An unreflected cell transfer between an input port of set N1 and anoutput port of set N2 is performed by distribution from the first stageto any of the switching elements in the second stage of the selectionunit, then this selection unit performs a distribution to any switchingelement in the third stage. In the third stage, the switching elementperforms a selective routing to one or more switching elements of thefourth stage, the fourth stage performing a selective routing to one ormore output ports of set N2.

- For an unreflected cell transfer in the other direction, from set N2to set N1, the first stage distributes each cell to one of the switchingelements of the next stage. In this transfer direction, this next stageperforms a selective routing to one or more of the m two stage selectionunits, at the same time freely selecting one of the switching elementsof the first stage in each destination selection unit. In a switchingelement of the third stage, a selective routing transfers the cell toone or more switching elements of the fourth stage, the fourth stageperforming a selective routing to one or more output ports of set N1.

- For a reflected transfer between an input and an output port of thesame set N2 or the same subset N'1 of a selection unit, the reflectionfunction occurs either in the first, or in the second stage as in thenetwork in FIG. 9.

- On the other hand, for a reflected transfer between an input port andan output port of the same set N1, but of two different selection units,the reflection function is possible only in the third stage whichinterconnects the m selection units. In this case, the first stageperforms a distribution to the switching elements of the second stage;the second stage also performs a distribution to the switching elementsof the third stage; the third stage then reflects the transfer andperforms a selective routing to one or more destination selection units,at the same time leaving a free choice between the switching elements ofthe second stage in each selection unit concerned. Then, the switchingelement of the second stage performs a selective routing to one or moreswitching elements of the first stage, the first stage performing aselective routing to one or more destination output ports of the setN'1.

This example of a switching network illustrates once again the factthat, according to the invention, the groups of outlets constructed inthe switching elements of the switching network are not the sameaccording to the stage into which they belong and account is taken ofthis in the routing mode implemented in each stage although the routinginformation of the cell remains the same in all stages.

Turning now to FIG. 11 which represents a unidirectional switchingnetwork composed of selection units which comprise input terminal unitsTSUi, selection planes PS and output terminal units TSUo, in eachselection unit, there are switching elements which can be of the type inthe previous figures, each represented by the customary sign of aswitching matrix, with, on the left, the number of inlets of theswitching element and, on the right, the number of outlets of theswitching element. These switching elements are interconnected by links.

Within an input terminal unit TSUi1, for example, there are two stagesof switching elements, switching elements TSi1 to TSi16 and switchingelements ASi1 to ASi4. There are in general one or more links between anoutlet of a switching element of the first stage and an inlet of aswitching element of the second stage. The four outlets of a switchingelement of the first stage, TSi1 for example, are then each connected toone or more inlets of each of the four switching elements of the secondstage. In the case of a single link, the 16 inlets on a switchingelement of the second stage, ASi1 for example, are each connected to anoutlet of each of the 16 switching elements of the first stage. The 16×4inlets of the switching elements of the first stage are connected to 64input ports pi1 to pi64. The other input terminal units can be similar,except for the numeric values indicated. In this example, the outputterminal units are assumed to be constructed in the same way andsymmetrically. Thus the output terminal unit TSUo1, for example, givesaccess, via the two stages of switching elements comprising theswitching elements ASo1 to ASo4 and TSo1 to TSo16, to output ports po1to po64.

The figure also represents input and output terminal units TSUi128 andTSUo128, to indicate a total number of terminal units in the switchingnetwork.

The selection planes, such as the selection plane PS1, comprise threeselection stages formed from PSi1 to PSi32, PSc1 to PSc16, PSo1 toPSo32. The arrangement of internal links between one stage and the nextobeys the same principle as the terminal selection unit, assuming inthis example a number of links between switching elements equal to 1;this will not be described in detail.

There are 16 selection planes PS1 to PS16. The 16 outlets of a switchingelement of the second stage of an input terminal selection unit TSUi1for example, are individually connected by 16 links to an inlet of eachof the 16 selection planes. The four outlets of the same rank of thefour switching elements of an input terminal unit, TSUi1 for example,are connected to successive inlets of the same switching element, PSi1for example, of a selection plane, PS1 in this instance. Therefore, the512 inlets of a selection plane, PS1 for example, are connected, infours, to the four switching elements of the second stage of each of the128 input terminal units.

The construction of the links between the outlets of the switchingelements of the first stage of the selection planes, PSo1 to PSo32 forthe selection plane PS1 for example, and the inlets of the switchingelements of the first stage of the output terminal units is symmetricalwith that which has just been described.

When the entire switching network is symmetrical with respect to thecentral stage of the selection planes, that is when the number ofswitching element inlets and outlets and the number of counterpart linksare identical, it is possible to construct an equivalent foldedswitching network, with bidirectional switching elements at least forpart of the stages, as represented in FIG. 12 and described below. Eachcentral switching element, such as PSc1, is linked by three switchingstages on each side to all the input ports and all the output ports.Conversely, between any input port and any output port, there are inthis example more than 4 000 (4 k) separate paths passing through one ofthe four switching elements ASi of the incoming selection unit, one ofthe 16 selection planes PS, one of the 16 central switching elements PScin a plane, and one of the four switching elements AS0 of the outgoingselection unit. Taking into account the total accessibility of eachinput port to all the central switching elements PSc of all the planes,the transfer in this first part of the network effects a generaldistribution of all the incoming traffic over all 16×16 centralswitching elements PSc, therefore a complete distribution of all theincoming cell traffic.

Then, from the central stage PSc to the output ports, routing isnecessarily selective, to reach the destination output port or ports. Ifit is desired to reach several separate output ports, in apoint-to-multipoint routing, this selective routing must comprise anumber of branches with one or more stages.

Referring now to the previous descriptions, with particular respect toFIGS. 1 and 3, a description follows of how the different routing modesare applied in the switching elements of the network in FIG. 11.

Consider first of all a point-to-point routing, for example between theinput port pi1 and the output port pol. In the cell header, routing modedata in the routing control code RCC specifies point-to-point routing.The output address RCA comprises seven bits denoting the terminal unitTSUo1 and six bits denoting the output port pol in the terminal unit.

In the switching elements of the first stage of the switching network,such as TSi1, the routing parameters are such that the cell is forwardedto one of the set of all the outlets of the switching element. Theconditions of this selection have already been examined. For example,the cell is thus forwarded to switching element ASi1.

In the switching elements of the second stage of the switching network,such as ASi1, the routing parameters have the same effect as in thefirst stage and the cell is thus forwarded to one of the set of all theoutlets of the switching element, for example that which leads to theplane PS1 and therefore, in PS1, to the switching element PSi1.

The same applies in the switching elements of the third stage of theswitching network and the cell reaches for example switching elementPS1.

From the central stage, routing becomes selective, at least in part.

The routing parameters of the switching elements of the central stage ofthe switching network are such that the switching element PSc1 selects agroup of four terminal units in which the destination terminal unit islocated, on the basis of five bits, out of the seven bits denoting theterminal selection unit, which denote the routing group, in the presentexample a single outlet, leading to that of the 32 switching elements ofthe fourth stage of the switching network which, in plane PS1, accessthe destination terminal unit. In this way a link is selected leading tothe switching element PSo1.

The operating mode is similar to that which has just been examined inthe switching elements of the fifth stage of the switching network. Therouting parameters are different; they lead to the selection of the tworemaining bits of the identity of the destination terminal unit, whichidentify a routing group comprising the four outlets leading to the fourswitching elements ASo1 to ASo4, according to the example in question.One of these four outlets is selected as described previously. It leadsthe cell, for example, to switching element ASo1.

In the switching elements of the sixth stage of the switching network,the routing parameters select, from the six bits of the address RCAdenoting the output port, the four bits identifying the switchingelement of the last stage serving this output port. The cell is thus ledto the switching element TSo1, in accordance with the example selected.

Finally, in a similar manner, in the switching element of the last stageof the switching network, the routing parameters will enable the cell tobe transferred to output port PO1.

During this point-to-point transfer sequence, the routing parameters ofthe switching elements of the different stages have therefore first ofall enabled the cell to be transferred non-selectively to any switchingelement of the central stage, then transferred selectively, usingsuccessive parts of the output address RCA, to the destinationindicated.

It is easy to verify that, insofar as all the switching elements of thecentral stage, in a selection plane, see the 32 switching elements ofthe fifth stage of this selection plane in the same way, the routing isidentical in each of them. Similarly, insofar as all the selectionplanes see the output terminal units in the same way, it can beconcluded that all the switching elements of the central stage performthe routing in the same way. Similar reasoning leads to the sameconclusion with respect to the switching elements of the other stages,from the fifth to the last. The conclusion is, in such an example of afolded switching network, that the routing parameters depend only on theidentity of the stage in which the switching element is located, not onits position in the stage.

However, it could also depend on the position of the switching elementin the stage, in certain variants of this type of switching network, forexample such that the set of terminal units of the set of selectionplanes does not consist of selection units of identical configuration,as is the case, for example, during switching network extensionoperations requiring progressive changeover from one configuration toanother.

In addition, it should be emphasised that successive cells, from thesame source and with the same destination can, mainly through thedistribution routing practiced in the first stages of the switchingnetwork, take a large number of different paths, which implements adistribution of regular and irregular traffic streams, favourable to themore even handling of the varied cell throughputs submitted to theswitching network and therefore the relative performance of the celltransfer function.

Point-to-multipoint routing, in such a network, is performed on the samebasis, except that in some or all selective routing stages, the cell isreplicated and forwarded to different groups of outlets in the switchingelements of the stage in which the multicast tree indicates that severaloutgoing branches are required to the next stage.

This example illustrates how point-to-multipoint transfers according topredetermined multicast trees can be implemented according to theinvention in multiple path, self-routing networks, retaining for thistype of transfer the possibility of choosing a path from any one toseveral ports from the multiplicity of possible paths across theswitching network, through a characteristic organisation of the contentof the multicast tree memories of the switching elements of thedifferent stages. According to the invention, it is possible to definecorresponding branch points such that no unnecessary copy is generatedin any stage, which avoids any internal overloading of the internallinks between stages. This characteristic is implemented according tothe following principles:

- the absence of copy in the distribution stages;

- the same content (branch points) of the multicast tree memory in allthe switching elements of a stage which belong to a particular set ofequivalent multiple paths for routing the cells to the groups ofswitching elements of the next stage;

- in these "equivalent" switching elements which perform a selectiverouting over different and separate routing groups, a branch to severalpredetermined routing groups (in the multicast tree memory) is performedby transferring a copy of the incoming cell only to the routing groupsmarked as branches required in the switching elements out of the set ofpossible routing groups. Thus, no unnecessary copy is generated in eachstage.

FIG. 12 represents the folded version of the network in FIG. 11,obtained using at least for one part stages of bidirectional switchingelements, other than for the central stage PSc which remainsunidirectional. By analogy with the notation used, it is clear that thecounterpart switching elements can now be merged in bidirectionalstages, as follows:

- the previous stages 1 and 7 (TSi and TSo) become the firstbidirectional stage (TS),

- the previous stages 2 and 6 (ASi and ASo) become the secondbidirectional stage (AS),

- the previous stages 3 and 5 (PSi1 and PSo1) become the thirdbidirectional stage (PSa).

However, the central stage PSc remains unidirectional and this fourthstage is referred to as the mirror stage (mandatory reflection).

The set of characteristics and properties of the unidirectional networkin FIG. 11 can easily be transferred to that of the folded version:

- The same number of possible paths exists without counting theadditional paths rendered possible by the intermediate reflectionfunctions described below.

- The two major processes in the transfer of a cell, generaldistribution and selective routing, are also implemented by referringnow to a first transfer part in the incoming direction up to thereflection stage and a second transfer part in the outgoing directionfrom the latter up to the first stage, the routing operations at eachstage easily being transposed by symmetry and being based on the sameprinciples as those described for the network in FIG. 11.

However, the folded variant in FIG. 12 presents the following additionalcharacteristics derived from the intrinsic reflection facilitiespossible in a bidirectional switching element as described previously:

- In the first part of a point-to-point transfer in which the cell isfreely distributed in the incoming direction to one of the switchingelements of the next stage, in each bidirectional stage, potentially TS,AS and PSa, a premature reflection is possible whenever the destinationoutput port is accessible by the switching element in question, and ofcourse if the latter is bidirectional. Such a premature reflection istherefore possible:

- in the first stage TS if the destination port belongs to the group ofports connected to the switching element in question TSx,

- in the second stage AS if the destination ports belongs to theterminal unit in which the switching element in question ASx is located,

- in the third stage PSa if the destination port belongs to the group offour terminal units to which the switching element in question TSax isconnected.

- Said premature reflection possibilities induce the followingcharacteristic properties:

- a relative reduction of the load on the internal links insofar as partof the cell traffic does not pass through all the stages of theswitching network,

- an increase in the number of possible paths, that is the prematurelyreflected paths,

- the possibility of underequipping the switching network in the figurein terms of the number of stages and to proceed with successiveextensions of stages without altering the wiring between stages, insofaras each bidirectional stage 1, 2 or 3 can temporarily form the lastequipped stage and then perform the mandatory reflection functions of amirror stage.

While the principles of the invention have been described above inconnection with specific apparatus and particular numerical figures, itis to be clearly understood that description is made only by way ofexample and not as a limitation on the scope of the invention.

I claim:
 1. Cell-based multiple path, self-routing switching network forswitching asynchronous time division multiplex cells of fixed orvariable length, said switching network comprising:a plurality of inputports; a plurality of output ports; a plurality of switching elementsarranged in several stages of interconnected switching elements, whereineach of said switching elements has inlets and outlets arranged totransfer a cell received on one of its inlets to one or more of itsoutlets according to routing information associated with said cell, theinput ports are coupled to respective said inlets of the switchingelements of an input stage, the output ports are coupled to respectivesaid outlets of the switching elements of an output stage, eachswitching element of at least one stage of the network has at leastthree said outlets, said at least three outlets are arranged in at leasttwo predetermined groups of said outlets, at least one group of saidpredetermined groups of outlets comprises at least two said outlets, andsaid each switching element further comprisesmeans for identifying, onthe basis of routing information data associated with a cell received atany one of its inlets, a set comprising one or more of saidpredetermined group of said outlets, and means for transferring saidreceived cell to a respective selected outlet of each of said one ormore of said outlet groups of the thus identified set.
 2. Switchingnetwork according to claim 1, whereineach of the switching elements of astage other than said at least one stage has at least three outletsarranged in at least one predetermined group of outlets in anarrangement different from that of the outlets of said at least onestage into said at least two predetermined groups of outlets, and saideach of the switching elements of said at least one stage and of saidother stage further comprisesmeans for holding its own routingparameters derived from position information depending on the stage inwhich said each switching element is located, and means for using saidown routing parameters to determine the arrangement of its ownrespective outlets in its own respective predetermined routing group orpredetermined routing groups.
 3. Switching network according to claim 2whereinsaid position information also depends on the location of saideach switching element in its respective said stage.
 4. Switchingnetwork according to claim 2, whereinsaid each stage further comprisesmeans for interpreting said own routing parameters to determine whethera received cell is to be transferred to the outlets of the switchingelement in a point-to-point routing mode or a point-to-multipoint mode,and said interpretation is based on said routing parameters. 5.Switching network according to claim 1, whereinthe switching elements ofat least certain stages of the network includes means for interpretingrouting information contained in a routing tag of a cell, and saidrouting information include a routing control code defining the requiredsequence for transferring the cell across the switching network, anoutput port address, for a point-to-point routing, and/or a multicasttree internal reference number for a point-to-multipoint routing. 6.Switching network according to claim 5, wherein said switching elementsinterpreting said routing control code on the basis of said routingparameters implement as a result of thereof a point-to-point routingmode or a point-to-multipoint routing mode.
 7. Switching networkaccording to claim 1, wherein the switching elements of at least onestage are asymmetric, each implementing an expansion of the trafficentering the stage thereby reducing the cell traffic load of the outletsof these switching elements with respect to their inlets.
 8. Switchingnetwork according to claim 1, wherein the switching elements of at leastone stage are asymmetric, each implementing a concentration of trafficleaving the stage, thereby increasing the cell traffic load of theoutlets of these switching elements with respect to their inlets. 9.Switching network according to claim 1, whereinthe switching elements ofat least a first stage are asymmetric, each implementing an expansion ofthe traffic entering the stage, reducing the cell traffic load of theoutlets of these switching elements with respect to their inlets, andthereby achieving a reduction in the traffic load within the switchingnetwork between these two types of switching stages of asymmetricswitching elements.
 10. Switching network according to claim 9, whereinthe expansion rate in at least one of the first stages is exactlycompensated for by the concentration rate in at least one of the laststages, thereby implementing a symmetrical switching network having thesame number of input and output ports.
 11. Switching network accordingto claim 1, whereinall the switching stages are asymmetrical, having thesame number of inlets and outlets, and the switching network istherefore also asymmetrical, having the same number of input ports andoutput ports.
 12. Switching network according to claim 5, whereinatleast certain stages are bidirectional switching stages for routingcells belonging to two opposing traffic streams, in each of theswitching elements of each of the bidirectional switching stages, theinlets are divided into two sets of inlets and the outlets into two setsof outlets, one traffic stream normally being routed from a first set ofinlets to a first set of outlets and the other traffic stream from asecond set of inlets to a second set of outlets, and the interpretationof the routing information in the switching element of a bidirectionalswitching stage takes account of the traffic stream to which it relates.13. Switching network according to claim 4, wherein all the stages ofthe switching network are unidirectional, routing cells belonging to asingle traffic stream routed.
 14. Switching network according to claim13, whereinsaid network includes at least three said stages, eachswitching element of a stage other than the last is connected by one ormore links to each switching element of a following stage, and eachswitching element of one stage other than the first is connected by oneor more links to each switching element of a preceding stage. 15.Switching network according to claim 13, whereinsaid network furthercomprises at least two selection units including at least one inletselection unit and at least one outlet selection unit, each saidselection unit is formed of selection unit switching elements arrangedin at least two selection unit stages, each selection switching elementof a selection unit stage other than the last is connected by one ormore links to each selection unit switching element of the followingselection unit stage, each selection unit switching element of aselection unit stage other than the first is connected by one or morelinks to each selection unit switching element of a preceding selectionunit stage, the inlet selection units are disposed in tandem with theoutlet selection units, the input ports are connected to the inlets ofthe inlet selection units, and the output ports are connected to theoutlets of the outlet selection units.
 16. Switching network accordingto claim 15, further comprising selection plane selection units forconnecting inlet selection unit outlets to outlet selection unit inlets.17. Switching network according to claim 13 wherein, in theunidirectional switching elements of at least one stage, one of saidgroups of outlets contains all of the outlets, for a generaldistribution of the incoming traffic over all the outlets of this stagein the incoming transfer direction.
 18. Switching network according toclaim 12, whereinsaid switching network is configured as an extensiblefolded network having at least two stages, the first stage is abidirectional stage which functions as said input stage and also as saidoutput stage, the input ports are connected to the inlets of said firstset of inlets of the switching elements of the first stage, the outputports are connected to the outlets of said second set of outlets ofthese same switching elements of the first stage, and the last stage isa unidirectional switching stage which routes an incoming traffic streamto the switching elements of a preceding stage, thereby implementing atraffic reflection function.
 19. Switching network according to claim12, wherein said switching network is configured as an extensiblefoldednetwork having at least three stages at least one of which isbidirectional, the first stage functions as said input stage and also assaid output stage and consists of two sets of counterpart unidirectionalswitching elements, one incoming, the other outgoing, the input portsare connected to the inlets of said set of unidirectional incomingswitching elements of the first stage, the output ports are connected tothe outlets of said set of unidirectional outgoing switching elements ofthe same first stage, and the last stage comprises unidirectionalswitching elements which route an incoming traffic stream to theswitching elements of a preceding stage, thereby implementing areflection function.
 20. Switching network according to claim 18,whereineach switching element of a stage other than the last stage isconnected by one or more links to each switching element of a followingstage, and each switching element of a stage other than the first stageis connected by one or more links to each switching element of apreceding stage.
 21. Switching network according to claim 12,whereinsaid switching network is configured as an extensible foldednetwork having at least four stages, at least one of which isbidirectional, at least the first two stages of the switching networkcomprise inlet and outlet selection units each formed from switchingelements arranged in at least two selection unit stages, each saidswitching element of one selection unit stage other than the last isconnected by one or more links to each switching element of a followingselection unit stage, each said switching element of one selection unitstage other than the first is connected by one or more links to eachswitching element of a preceding selection unit stage, and the laststage of the switching network is a unidirectional switching stage whichroutes an incoming traffic stream to the switching elements of apreceding stage, thereby implementing a reflection function. 22.Switching network according to claim 21, wherein the inlet and outletselection units are interconnected by at least two selection planes,each comprising an arrangement of one or more stages according to therequired capacity of the switching network.
 23. Switching networkaccording to claim 22, wherein the increase in capacity of saidextensible network is achieved by adding successive stages withoutaltering the wiring between stages, each intermediate configuration offewer stages using as its last installed stage a stage of bidirectionalswitching elements which can implement a reflection function in the laststage of the folded network.
 24. Switching network according to claim12, whereinsaid switching network is configured as an extensible foldednetwork having at least three stages at least one of which isbidirectional, the input ports are connected to inlets of the switchingelements of a first stage which functions as said input stage, theoutput ports are connected to outlets of the switching elements of thesame first stage which also functions as said output stage, the laststage comprises unidirectional switching elements which route anincoming traffic stream to the switching elements of a preceding stage,thereby implementing a reflection function, and the switching elementsof one or more of the first stages of the switching network are arrangedso that, in the incoming traffic routing direction and when the routingdata specifies a point-to-point routing and/or a point-to-multipointrouting, and taking into account said routing parameters, there is ageneral distribution of the incoming traffic.
 25. Switching networkaccording to claim 1, wherein, in said each switching element, any cellto be transferred from one of the outlets of a selected said routinggroup of outlets is provided at a selected outlet of said selectedrouting group.
 26. Switching network according to claim 25, wherein thecell load is balanced over all the outlets of said routing group. 27.Switching network according to claim 25, wherein a quasi orpseudo-random distribution process is used to select the selected outletin order to achieve a decorrelation between the distribution of cellsover the inlets and the distribution of cells over the outlets of saideach switching element.
 28. Switching network according to claim 13,wherein said switching network further comprises two asymmetricunidirectional networks each having a respective three counterpartstages, the first unidirectional network interconnecting N1 input portsto N2 output ports, the second unidirectional network connecting N2input ports to N1 output ports, juxtaposed so as to achieve theequivalent of a switching network interconnecting in both trafficdirections, on one side N1 input and output ports and on the other, N2output and input ports.
 29. Switching network according to claim 12,whereinthe switching network comprises at least three said stages atleast one of which is bidirectional, said at least three stages arearranged to form a non-folded bidirectional network interconnecting afirst set of N1 input and output ports and a second set of N2 output andinput ports, each switching element of an internal stage is connected tothe switching elements of the preceding and following stages by one ormore links, each switching element of an end stage is connected on oneside to the switching elements of the adjacent stage and, on the other,to one of the sets of input and output ports, and the cells aretransferred between an input port and an output port belonging either tothe two different sets of ports, through transfer across the threestages, or to the same set of ports through reflected transfer in one ofthe switching elements of a bidirectional stage, permitting theinterconnection of these two ports.
 30. Switching network according toclaim 29, whereinit contains at least four stages, wherein at least thefirst two stages, adjacent the set of N1 input and output ports,consists of inlet and outlet selection units each formed from switchingelements arranged in at least two stages, at least one stage, adjacentthe set of N2 input and output ports interconnects firstly, this set ofN2 ports and, secondly the selection units giving access to said N1ports, and the switching elements of successive stages areinterconnected by one or more links.
 31. Switching network according toclaim 22, whereinthe number of said selection planes is selected on thebasis of the highest cell traffic load averaged over the set of inputand output ports of each selection unit, the use in the calculationexclusively of these average values being made possible by thedistribution of traffic over a multiplicity of paths in each selectionunit.
 32. Switching network according to claim 6, whereinsaid switchingelements of said at least one stage each further an associated branchpoint memory, and the identities of the outlet groups corresponding tothe branches to be performed in a switching element, when it is tooperate in a point-to-multipoint routing mode are obtained by readingthe associated branch point memory using said multicast tree internalreference number.
 33. Switching network according to claim 32,whereinthe contents of the branch point memories of the switchingelements of the different stages are marked so that only those of theswitching elements effecting a selective routing contain branchingindications necessary for the stage in question for the multicast treein question, no branching indication is marked in the switching elementsof the stages effecting a general traffic distribution, and thedifferent switching elements which belong to a set of equivalentswitching elements in respect of the internal paths between stages,possess the same branch point content for each multicast tree, therebyavoiding the generation of unwanted copies of cells in the switchingnetwork.
 34. Switching network according to claim 32, wherein saiddistribution tree does not depend on the input port but only on the setof output ports to which a cell from any input port is to betransferred.
 35. Switching network according to claim 1, wherein atleast some of the switching elements are switching modules each of whichis composed of several elemental switching elements arranged so thatsaid switching module presents at its input and output access points thecharacteristics and performances of a single virtual switching elementhaving a greater number of inlets and outlets than a single saidelemental switching element.
 36. Switching network according to claim 1,wherein said cells are packets.
 37. Switching network according to claim1, wherein said cells are cells of fixed or variable length consistingof a number of fixed length subcells.
 38. Switching network according toclaim 1, wherein said routing information associated with the cell iscontained in the cell itself.
 39. Switching network according to claim2, whereinthe arrangement of said outlets in said groups is different insaid at least two stages.
 40. Switching network according to claim 2,whereinthe arrangement of said outlets in said groups is the same insaid at least two stages.
 41. Switching network according to claim 2,wherein said position information is independent of the location of saideach switching element in its respective said stage.
 42. Switchingnetwork according to claim 12, wherein, in the switching elements of atleast one bidirectional stage, one of said groups of outlets containsall the outlets of one of the two sets of outlets for one of the twotransfer directions, for a general distribution of the incoming trafficover all the outlets of this stage in the incoming transfer direction.43. Switching network according to claim 1, wherein said set of groupsincludes at least two of said groups.